The invention relates to an integrated circuit in complementary circuit technology comprising a substrate bias voltage generator which generates a negative substrate bias voltage connected to a semconductor substrate within which the complementary circuit technology is integrated.
In circuits of this type, the semiconductor substrate does not lie at the ground potential V.sub.SS of the circuit, but at a substrate bias voltage V.sub.BB which is generatetd by means of a substrate bias voltage generator. Given a semiconductor substate of p-conductive material that is provided with an inserted, n-conductive tub-shaped semiconductor zone, a negative substrate bias voltage of about -2 to -3 volts is employed. The source regions of field effect transistors which are provided on the semiconductor substrate outside of the tub-shaped semiconductor zone are placed at the ground potential V.sub.SS.
At the moment the supply voltage V.sub.DD is switched on, the p-conductive semiconductor substrate under consideration is first in a "floating" state in which it is disconnected from external potentials. Via the depletion layer capacitances which are present, the substrate can be temporarily charged to a positive bias voltage which remains until the substrate bias voltage generator takes effect and is replaced by the negative substrate bias voltage gradually building up at the output of the generator.
These depletion layer capacitances lie, first, between the tub-shaped semiconductor zone and the substrate and, second, between the source regions lying on the ground potential and the substrate. During operation of the integrated circuit as well, however, greater currents which are diverted from the semiconductor substrate via the substrate bias voltage generator to a terminal lying at ground potential can also lead to a positive bias voltage of the semiconductor substrate due to the voltage drop at the internal resistor of the substrate bias voltage generator. Positive bias voltages, however, represent a high safety risk for the integrated circuit, since a "latch-up" effect which generally means the outage of the integrated circuit can be triggered.
For an understanding of the "latch-up" effect, it can be assumed that four successive semiconductor layers of alternating conductivity type are generally provided between a terminal of a field effect transistor of the first channel type lying in the tub-shaped semiconductor zone and a terminal of a field effect transistor of the second channel type placed on the semiconductor substrate outside of this zone. The one connecting region of the former transistor forms the first semiconductor layer, the tub-shaped semiconductor zone forms the second layer, the semiconductor substrate forms the third layer, and the one connecting region of the latter transistor forms the fourth semiconductor layer. Given a positive bias voltage of the semiconductor substrate, the pn-junction between the third and the fourth semiconductor layers can be biased to such a degree in a conducting direction that a current path arises between the transistor terminals, this current path being attributed to a parasitic thyristor effect within this four-layer structure. Even after the positive bias voltage disappears, the current path remains in existence and can thermally overload the integrated circuit.